In the current state of integrated circuit technology, an integrated circuit device will often be in the form of a chip. Such a chip sometimes will be mounted onto a leadframe to form a package. Interconnecting the chip with a leadframe, and components external to the package, may sometimes involve interconnecting bond pads of the chip with bonding fingers around the periphery of the leadframe, which may then form the pin-out. The pins may be in the form of, for example, external leads or bond pads, and may electrically interconnect the package with external components such as, for example, another package.
The pin-out of a package may depend on the signaling, power, and ground requirements for the die inside the package. In interconnecting the package to another package, certain pins may be required, and the other package may also require certain pins for the interconnection. Thus, this type of interconnection affects the ultimate pin-out count for each package.
In addition to an increased pin-out count, multiple packages on a system level board may consume an undesirable amount of so-called “real estate.” Resultantly, the size of a device incorporating the board having the packages mounted thereon may be affected. Certain functionalities may need to be sacrificed in order to balance against the size demands.
Efforts have been made to remedy these problems. For example, multiple-chip leadframes have been designed, the leadframes including multiple die paddles for mounting the dies thereon. Unfortunately, manufacturing these leadframes may add cost in terms of time and money due to the leadframes having to be specially designed. As a result, sometimes multichip packages are forgone altogether, and standard single-chip packages are used instead. This solution, however, fails to reduce the spacing impact (and associated cost) on the system level board, nor does this solution reduce the complexity of packaging operations.